Multiple phase motors are powered by a driver that provides current and voltage to each of the phases of the motor in proper sequence. For example, a three-phase motor consists of sets of motor leads that are driven 120 degrees out of phase with one another to cause motor rotation. The driver of the motor, such as a field effect transistor (FET), may be controlled by a state machine with many states. For example, a state machine for a three-phase motor in a hard drive has six states. Each state controls the current flowing from one phase of the motor to another. To efficiently drive the motor and to minimize the mechanical vibration, the state machine must progress through the states in a certain sequence and change the states at a certain rate. The rate of change of the states is controlled by a clock.
In one example, a phase locked loop (PLL) is used to generate the clock that matches the rotation rate of the motor. To this end, the back electromotive force (BEMF) signal from motor is compared with the generated clock from the phase lock loop. The error generated from this comparison of the frequency and phase of the clock signal to the frequency and phase of the BEMF signal is used to adjust the phase lock loop to cause the clock signal to match the motor BEMF signal. This closed-loop control system continually adjusts the phase lock loop such that the generated clock signal can be accurately locked to the frequency and phase of the BEMF of the motor.